Sneh Saurabh obtained his PhD from IIT Delhi in the year 2012 and B.Tech. (EE) from IIT Kharagpur in the year 2000. He worked in the semiconductor industry for around sixteen years, before joining IIIT Delhi in June 2016. He has contributed at various technical and managerial positions at Cadence Design Systems, Synposys India, Magma Design Automation and Atrenta India. He has expertise in the areas of Static Timing Analysis, Design Implementation, Logic and Physical Synthesis, Timing Optimization and Formal Verification. His work in the industry has centered on tackling challenges that arise due to scaling of transistors and the associated fall-out on the complexity of IC design and verification. His current research interests are in the areas of Nanoelectronics, Exploratory Electronic Devices, Energy-Efficient Systems and CAD for VLSI. He holds three US patents and he is the coauthor of the book titled "Fundamentals of Tunnel Field-Effect Transistors". He received Early Career Research Award by Science and Engineering Research Board (SERB) in 2017. He was recognized for Teaching Excellence multiple times for the courses VLSI Design Flow and Introduction to Nanoelectronics. Currently, he is on the editorial board of IETE Technical Review and Senior Member, IEEE.
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